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Revision 0.1
OMAP4460 Pandaboard ES
System Reference Manual
September 29, 2011
DOC-21054
With an external power supply plugged in, the 5Vdc input power is supplied from the input DC jack at
P3. The current capability in this mode is only limited by the particular DC supply being used. The path
of current flow in this mode is designated below by the blue arrows. The switch at U21 will be disabled
by the insertion of the DC input jack in this mode, and the regulated 5Vdc from the wall supply will be
connected to the input of the TPS54320 switching power supply at U22, which provides a 3.7V “battery”
voltage for the TWL6030 and TWL6040 Companion ICs.
CAUTION: only use a 5Vdc regulated power supply to power the
Pandaboard ES. Connecting a supply with an output higher than +5Vdc
could cause possible board damage.
The supervisor IC at U19 has the DC input power tied to its VDD pin through a voltage divider. When
the voltage at the VDD input of this IC exceeds 1.40V (i.e. DCIN_JACK > 5.64V), the reset output of the
supervisor is negated. This will enable the two FETs at T1A and T1B, which will illuminate the red
overvoltage indicator, and disable the load switch at U16, which removes input power to the onboard
circuitry. The load switch at U14 that provides 5V USB Host power is enabled and disabled manually by
writing GPIO_1 to a ‘1’, or a ‘0’, respectively. This load switch powers up disabled.
2.8.2
USB/Ethernet Power Circuitry
There is a fixed 3.3V LDO (U11) that provides power for the LAN9514 Ethernet/USB Hub device. This
device is a Texas Instruments TPS73633DBVR device which can provide up to 400mA of output current.
This device may be controlled via S/W by writing OMAP4460 GPIO_1. Writing this GPIO high will
enable this LDO, while writing it low will disable it (see Table 10 on page 41). This device is shown on
sheet 11 of the schematic.
2.9
Standard Volatile Memory
The OMAP4460 processor supports two LPDDR2 channels, accessible only via a POP memory device
soldered on the 216-ball, 12x12 mm footprint on top of the OMAP4460 processor. Each channel
supports up to two chip-selects, so up to four LPDDR2 memory dies are supported. The two stacked
memory packages are directly connected to the two LPDDR2 EMIF4D interfaces of the OMAP4460 die.
The base address for the LPDDR2 is 0x8000 0000.
An 8Gb/1GB POP LPDDR2 DRAM device (Elpida P/N EDB8064B1PB-8D-F) is provided on the
Pandaboard ES. The memory device has four dies, with each die being a separate 2Gb LPDDR2.
Page 27 of 82
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